It is often the case with semiconductors, circuit boards, and other digital circuitry having digital signal processing functions that digital signals of a predetermined pattern are input from the outside and the operation of the circuit is controlled or output signals are detected and function tests are conducted. By means of this type of control and testing, a plurality of signal pattern types are often needed for the signals that are input from the outside, and it becomes necessary to flexibly change the signal pattern in accordance with changes in control conditions or testing conditions. Therefore, attention is being focused on systems with which a signal pattern is generated by executing a program in which the signal pattern to be generated is entered by a processor as a signal generator for generating digital signal patterns.
A typical conventional signal generator is shown in FIG. 2. A signal generator 26 consists of a memory 20, a processor 23 connected to memory 20, and a signal output circuit 24 to which the output of processor 23 is connected. A pattern generation program 21 in which the signal pattern is entered and pattern data 22 that serve as the basic signal pattern are stored in memory 20. An example of pattern generating program 21 and pattern data 22 is shown in FIGS. 3(a) and (b), respectively. Processor 23 executes pattern generation program 21 in synchronization with clock signals and generates a signal pattern. Signal output circuit 24 converts the signal pattern generated by processor 23 to electrical signals on the signal level of a device 25, which is the object under control or test, and outputs these signals to device 25.
Next, the operation of signal generator 26 in FIG. 2 will be described taking as an example operation during execution of the pattern generating program in FIG. 3. FIG. 4 is a drawing representing the execution commands for each clock signal, and the clock by which the signal pattern is output to device 25 is underlined. It should be noted that the DATA command in the program in FIG. 3(a) is the command to generate pattern data represented by the argument taken from pattern data 22. The LOOP command is the command for repeated execution of commands, from the LOOP command to the LOOP END command, by the number of arguments. The JSR command is the command to execute the subroutine of the argument. The STOP command is the command to stop the program.
When the pattern generation program is being executed, the DATA command of step 30 is executed at the first clock (clock 1) to generate signal pattern “0000” that is stored by processor 23 as DATA0 of pattern data 22. Next, the next clock (clock 2) is set such that the LOOP command of step 31 is executed and the step from the LOOP command (step 31) to LOOP END command (step 34) is repeated three times. The JSR command of step 32 is executed at clock 3 and subroutine SUB1 (steps 36 and 37) is called. The DATA command of step 36 is executed at clock 4 by calling this subroutine to generate signal pattern “1010” stored as DATA1 of pattern data 22. The RTN command of step 37 is executed at clock 5 and the system returns from the subroutine to the main routine.
The same operation is performed for subroutine SUB2 from clocks 6 through 8 to generate signal pattern “1111” that is stored as DATA2 of pattern data 22. An evaluation of loop frequency and loop processing are conducted by the LOOP END command at clock 9. Steps 31 through 34 have only been executed once at this point; therefore, [the system] returns to step 32 and executes the details of the second repetition. The second loop is performed at clocks 10 through 16 and when a third repetition has been completed at clocks 17 through 23, the pattern generation program is ended by the STOP command at clock 24.
As is clear from FIG. 4, the time of 24 clocks is necessary to execute the pattern generation program in FIG. 3(a). During this time, a signal pattern is generated at underlined clocks 1, 4, 7, 11, 14, 18, and 21. Therefore, when the timing by which each signal pattern is generated is taken into consideration, the time interval from when the signal pattern of clock 1 is generated to when the signal pattern of clock 4 is generated is three clocks, while the time interval from when the signal pattern of clock 7 is generated to when the signal pattern of clock 11 is generated is four clocks. Thus, there is a problem in that when the pattern generation program in FIG. 3 is executed by signal generator 26 in FIG. 2, the pattern generation intervals are not consistent.
The method whereby the pattern generation interval is held constant by entering pattern generation program 21 by the DATA command only as shown in FIG. 5 is a potential method for solving this problem. By means of this method, it is not necessary to process the other commands in between the DATA commands; therefore, signal patterns can be output at the same time interval as the DATA command processing time (one clock). However, there is a problem in that pattern generation program 21 becomes longer in proportion to the length of the signal patterns; therefore, the pattern generation program becomes extremely long and a large memory 20 becomes necessary when the same signal pattern is repeated several times.
Moreover, there is a technology such as that described in Patent Reference 1 whereby the signal pattern generation cycle is held constant by an appropriate placement in the program of the no-operation command (NOP command) for a predetermined time. However, the time needed for execution of the command varies with the type of pattern generation program 21 compiler or processor 23; therefore, a pattern generation program 21 that corresponds to the properties of signal generator 26 must be created for each device. In addition, programming must be performed while referring to the signal generation timing and high-performance programming technology therefore becomes necessary. Furthermore, there is a problem with this method in that residual signal pattern generation timing is combined with timing having the longest signal generation time interval, and the maximum frequency of the signal pattern therefore becomes from ⅓ to 1/30 of the clock signal frequency.
Therefore, there is a method wherein a FIFO memory 62 is used at the output, as with a signal generator 60 in FIG. 6. The signal generator 60 and the signal generator 26 in FIG. 2 differ in that FIFO memory 62 is disposed between the output of processor 61 and the signal output circuit 24 of signal generator 60 and this signal generator has the function of stopping the operation of processor 61 when FIFO memory 62 is full. However, the operation of the other structural elements is the same.
Prior to outputting signal patterns to device 25, signal generator 60 generates signal patterns and then outputs signal patterns in succession once a predetermined number of signal patterns have been stored in FIFO memory 62. When the output speed from FIFO memory 62 is faster than the signal generation speed of processor 61, signals are generated without restopping processor 61. However, if the DATA command continues and FIFO memory 62 becomes full, processor 61 is stopped until FIFO memory 62 again has free capacity.
Thus, by means of signal generator 60 in FIG. 6, signal patterns generated by processor 61 are stored in FIFO memory 62 and are then output from FIFO memory 62 to device 25 at predetermined cycles; therefore, it is not necessary to take the signal generation timing into consideration when creating the pattern generation program 21. Moreover, the signal output starts after a signal pattern has been prestored in FIFO memory 62; therefore, it is possible to output signal patterns at a faster frequency than with signal generator 26 in FIG. 2.
However, the capacity of FIFO memory 62 is finite; therefore, when pattern generation program 21 with a complex structure is executed, long FIFO memory 62 becomes empty during the execution of the signal pattern generation program and the signal patterns cannot be output at a predetermined cycle (default). If a FIFO memory 62, which large enough to prevent default, is loaded, the device will inevitably become larger, more complex, and more expensive. Therefore, it is necessary to optimize pattern generation program 21 in accordance with the FIFO memory 62 capacity and the ratio of the speed of pattern generation and pattern output, and with other system properties.